(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to reduce device degradation of an N channel, metal oxide semiconductor (NMOS), device, via use of a composite insulator spacer located on the sides of a gate structure.
(2) Description of Prior Art
Static random access memory (SRAM), cells comprised with two P channel, metal oxide semiconductor (PMOS), transistors, and four NMOS transistors, are being used for logic applications. However it has been found that the yield of this type of SRAM cell is deleteriously influenced by device current degradation occurring for the NMOS components of the SRAM cell. After about five seconds of a constant current stress, applied to the NMOS device, degradation of 50 percent or greater has been observed for the NMOS drain current (Id), and transconductance (Gm), values. The degradation has been attributed to the use of a silicon nitride spacer, located on the sides of the gate structures of the NMOS devices. The stress of the silicon nitride spacer, of about 1000 Angstroms in thickness, located on the sides of a polycide gate structure, and located on the region of source/drain adjacent to the channel region, can induce the unwanted increases in the NMOS Id and Gm characteristics during normal device operation resulting in performance as well as yield loss.
This invention will teach a method of forming a sidewall spacer for gate structures of SRAM devices, in which the degradation in the Id and Gm characteristic of NMOS devices, during normal device operation, is reduced, when compared to counterparts fabricated with only thick silicon nitride sidewall spacers. Shih et al, in U.S. Pat. No. 5,723,352, use a silicon nitridexe2x80x94silicon oxide sidewall spacer to optimize performance and reliability of MOSFET devices, however that prior art features the use of a thermally grown, underlying silicon oxide layer which would not form on the sides of the dielectric layers used as capping layers for the gate structures, needed for the present invention.
It is an object of this invention to fabricate an NMOS device for a SRAM cell.
It is another object of this invention to reduce degradation of NMOS device drain current and transconductance, during device operation, via use of a composite insulator spacer formed on the sides of a polycide gate structure.
It is yet another object of this invention to use a high temperature oxide (HTO), layer, as an underlying component of a silicon nitridexe2x80x94silicon oxide composite insulator spacer, on the sides of an NMOS gate structure.
In accordance with the present invention a method of forming a composite insulator spacer, on the sides of gate structures, located in an SRAM cell, featuring an HTO oxide layer as the underlying component of a silicon nitridexe2x80x94silicon oxide composite insulator spacer, is described. After formation of insulator capped, polycide gate structures on an underlying gate insulator layer, lightly doped source/drain regions are formed for both NMOS and PMOS devices, of the SRAM cell. A high temperature oxide (HTO), layer is next deposited, at a thickness between about 140 to 160 Angstroms, followed by the deposition of a silicon nitride layer. An anisotropic reactive ion etch (REE), procedure is then employed to define a composite insulator spacer, comprised of an overlying silicon nitride layer on the underlying HTO layer, on the sides of the NMOS and PMOS gate structures. Heavily doped source/drain regions are then formed for both NMOS and PMOS devices, with subsequent degradation of drain current and transconductance for the NMOS device reduced as a result of the use of the thin HTO component of the composite insulator sidewall spacer.